ASIC RTL Design
Dmholdings
Work from Office
Full Time
Min. 5 yearsJob Description
ASIC RTL Design
Position Description: Design Engineer (Architect)
Job Description
EXP- 12- 20 Yrs
- RTL Design Engineer for PCIe IP development team.
- Position is based in Noida/Bangalore
- The role would include design and support of the RTL of the PCIe IP solution of Cadence.
- The work involved will be working with the existing RTL, addition of new features into the RTL, ensuring various customer configurations are clean as part of verification regressions, supporting customers, ensuring design is clean for LINT and CDC design guidelines.
Position Requirements:
- BE/BTech/ME/MTech - Electrical / Electronics / VLSI with an experience as a design and verification engineer, with a large portion of the recent work experience on RTL design and development.
- RTL Design using Verilog is a must.
- System Verilog experience and experience with UVM based environment usage / debugging is required.
- AXI3/4/5 experience is a desired.
- PCIe experience is highly desirable. Prior experience in RTL design and implementation of complex protocols is a must.
- Prior experience in IP development teams would be an added advantage.
Be part of the Cadence High-Speed SerDes PHY IP Front end Design team responsible for -
- Defining microarchitecture of digital blocks involving microcontroller-based designs to meet specifications, optimized for performance metrics of timing, area, and power.
- Lead and also hands-on end-to-end ASIC design including RTL implementation and design processes of Lint/CDC/SDC definition/STA/Synthesis.
- Collaborate with cross-functional teams of Architecture, Verification, Physical Design, and Mixed Signal teams.
- Mentor junior members of the team.
- Drive high-performance team culture of discipline, agility, and excellence.
Requirements:
Education: Bachelors in Electronics Engineering with +7 years, or Masters +5 years, or Ph.D. + 2 years of relevant experience in Digital Design.
- Hands-on experience in micro-architecting digital blocks and RTL implementation in Verilog/SV.
- Hands-on experience in SDC definition, STA, Lint Checks, CDC, Synthesis, and trail PNR.
- Desired Protocols knowledge – Ethernet, USB, PCIe, MIPI(DPHY), HDMI/Display
- Working closely with Analog design teams to co-develop algorithms, develop interfaces, and modeling in Verilog RLM as well as design high-speed critical digital circuits and signal processing (DSP) blocks.
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